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Efficient state reduction methods for PLA-based sequential circuits

 

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Opened Access Efficient state reduction methods for PLA-based sequential circuits
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Author: Avedillo de Juan, María José
Quintana Toledo, José María
Huertas Díaz, José Luis
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 1992
Published in: IEE Proceedings E: Computers and Digital Techniques, 139 (6), 491-500.
Document type: Article
Abstract: Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems.
Cite: Avedillo de Juan, M.J., Quintana Toledo, J.M. y Huertas Díaz, J.L. (1992). Efficient state reduction methods for PLA-based sequential circuits. IEE Proceedings E: Computers and Digital Techniques, 139 (6), 491-500.
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URI: https://hdl.handle.net/11441/76511

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