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νMOS-based sorter for arithmetic applications

 

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Author: Rodríguez Villegas, Esther
Avedillo de Juan, María José
Quintana Toledo, José María
Huertas Sánchez, Gloria
Rueda Rueda, Adoración
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2000
Published in: VLSI Design, 11 (2), 129-136.
Document type: Article
Abstract: The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation.
Cite: Rodríguez Villegas, E., Avedillo de Juan, M.J., Quintana Toledo, J.M., Huertas Sánchez, G. y Rueda Rueda, A. (2000). νMOS-based sorter for arithmetic applications. VLSI Design, 11 (2), 129-136.
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Format: PDF

URI: https://hdl.handle.net/11441/76361

DOI: 10.1155/2000/57240

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