Artículo
nu MOS-based sorter for arithmetic applications
Autor/es | Rodríguez Villegas, Esther
Avedillo de Juan, María José Quintana Toledo, José María Huertas Sánchez, Gloria Rueda Rueda, Adoración |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2000 |
Fecha de depósito | 2018-06-21 |
Publicado en |
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Resumen | The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a ... The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation. |
Agencias financiadoras | Comisión Interministerial de Ciencia y Tecnología (CICYT). España |
Identificador del proyecto | TIC97-0648 |
Cita | Rodríguez Villegas, E., Avedillo de Juan, M.J., Quintana Toledo, J.M., Huertas Sánchez, G. y Rueda Rueda, A. (2000). nu MOS-based sorter for arithmetic applications. VLSI Design, 11 (2), 129-136. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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vMOS-based Sorter.pdf | 2.259Mb | [PDF] | Ver/ | |