dc.creator | Morgado García de la Polavieja, Alonso | es |
dc.creator | Río Fernández, Rocío del | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.date.accessioned | 2018-05-07T16:12:21Z | |
dc.date.available | 2018-05-07T16:12:21Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Morgado García de la Polavieja, A., Río Fernández, R.d. y Rosa Utrera, J.M.d.l. (2016). Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR. En IEEE International Symposium on Circuits and Systems (ISCAS) (1-4), Montreal, Canada: Institute of Electrical and Electronics Engineers. | |
dc.identifier.uri | https://hdl.handle.net/11441/74220 | |
dc.description.abstract | This paper presents the design and implementation
of a fourth-order band-pass continuous-time modulator intended
for the digitization of radio-frequency signals in softwaredefined-
radio applications. The modulator architecture consists
of two Gm-LC resonators with a tunable notch frequency and
a 4-bit flash analog-to-digital converter in the forward path and
a non-return-to-zero digital-to-analog converter with a finiteimpulse-
response filter in the feedback path. Both system-level
and circuit-level reconfiguration techniques are included in order
to allow the modulator to digitize signals placed at different
carrier frequencies, from 450MHz to 950MHz. A proper synthesis
methodology of the loop-filter coefficients at system level and
the use of inverter-based switchable transconductors allow to
optimize the performance in terms of robustness to circuit errors,
stability and power consumption. The circuit, implemented in 65-
nm CMOS, can digitise signals with up to 57-dB SNDR within a
40-MHz bandwidth, with an adaptive power dissipation of 16.7-
to-22.8 mW and a programmable 1.2/2GHz clock rate1. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE International Symposium on Circuits and Systems (ISCAS) (2016), pp. 1-4. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/ISCAS.2016.7527168 | es |
dc.identifier.doi | 10.1109/ISCAS.2016.7527168 | es |
idus.format.extent | 4 p. | es |
dc.publication.initialPage | 1 | es |
dc.publication.endPage | 4 | es |
dc.eventtitle | IEEE International Symposium on Circuits and Systems (ISCAS) | es |
dc.eventinstitution | Montreal, Canada | es |