Ponencia
Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR
Autor/es | Morgado García de la Polavieja, Alonso
Río Fernández, Rocío del Rosa Utrera, José Manuel de la |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2016 |
Fecha de depósito | 2018-05-07 |
Publicado en |
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Resumen | This paper presents the design and implementation
of a fourth-order band-pass continuous-time modulator intended
for the digitization of radio-frequency signals in softwaredefined-
radio applications. The modulator ... This paper presents the design and implementation of a fourth-order band-pass continuous-time modulator intended for the digitization of radio-frequency signals in softwaredefined- radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finiteimpulse- response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65- nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7- to-22.8 mW and a programmable 1.2/2GHz clock rate1. |
Cita | Morgado García de la Polavieja, A., Río Fernández, R.d. y Rosa Utrera, J.M.d.l. (2016). Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR. En IEEE International Symposium on Circuits and Systems (ISCAS) (1-4), Montreal, Canada: Institute of Electrical and Electronics Engineers. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Design of a Power.pdf | 2.357Mb | [PDF] | Ver/ | |