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Complementary tunnel gate topology to reduce crosstalk effects

dc.creatorNúñez Martínez, Juanes
dc.creatorAvedillo de Juan, María Josées
dc.date.accessioned2018-05-03T14:31:02Z
dc.date.available2018-05-03T14:31:02Z
dc.date.issued2017
dc.identifier.citationNuñez Martínez, J. y Avedillo de Juan, M.J. (2017). Complementary tunnel gate topology to reduce crosstalk effects. En Design of Circuits and Integrated Systems (DCIS) (1-5), Granada, 23-25 November 2016: Institute of Electrical and Electronics Engineers (IEEE).
dc.identifier.urihttps://hdl.handle.net/11441/73989
dc.description.abstractTunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)es
dc.relation.ispartofDesign of Circuits and Integrated Systems (DCIS) (2017), pp. 1-5.
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectTunnel transistorses
dc.subjectSteep subthreshold slopees
dc.subjectNoise couplinges
dc.subjectLow poweres
dc.subjectEnergy efficienyes
dc.subjectLow supply voltagees
dc.titleComplementary tunnel gate topology to reduce crosstalk effectses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.publisherversionhttps://doi.org/10.1109/DCIS.2016.7845264es
dc.identifier.doi10.1109/DCIS.2016.7845264es
idus.format.extent5 p.es
dc.publication.initialPage1es
dc.publication.endPage5es
dc.eventtitleDesign of Circuits and Integrated Systems (DCIS)es
dc.eventinstitutionGranada, 23-25 November 2016es

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