Ponencia
DOE based high-performance gate-level pipelines
Autor/es | Núñez Martínez, Juan
Avedillo de Juan, María José Quintero Álvarez, Héctor Javier |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2014 |
Fecha de depósito | 2018-05-02 |
Publicado en |
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Resumen | Domino dynamic circuits are widely used in
critical parts of high performance systems. In this paper we show
that in addition to the functional limitation associated to the noninverting
behavior of domino gates, there ... Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | TEC2010-18937
TEC2011-28302 |
Cita | Nuñez Martínez, J., Avedillo de Juan, M.J. y Quintero Álvarez, H.J. (2014). DOE based high-performance gate-level pipelines. En Power and Timing Modeling, Optimization and Simulation (PATMOS) 24th International Workshop (1-4), 29 Sept- 1 Oct. 2014: Institute of Electrical and Electronics Engineers. |
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