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Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

 

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Opened Access Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
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Author: Nuñez Martínez, Juan
Ginés Arteaga, Antonio José
Peralías Macías, Eduardo
Rueda Rueda, Adoración
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2016
Published in: Analog Integrated Circuits and Signal Processing, 89 (3), 593-609.
Document type: Article
Abstract: This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart par...
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Cite: Nuñez Martínez, J., Ginés Arteaga, A.J., Peralias Macias, E. y Rueda Rueda, A. (2016). Design methodology for low-jitter differential clock recovery circuits in high performance ADCs. Analog Integrated Circuits and Signal Processing, 89 (3), 593-609.
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URI: https://hdl.handle.net/11441/73806

DOI: 10.1007/s10470-016-0870-6

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