Ponencia
Low Power Implementation of Trivium Stream Cipher
Autor/es | Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2012 |
Fecha de depósito | 2017-10-04 |
Publicado en |
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ISBN/ISSN | 978-3-642-36156-2 0302-9743 |
Resumen | This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The de-sign was simulated with Modelsim, and synthesized with Synopsys in three CMOS ... This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The de-sign was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implemen-tations. The results show that the application of the technique reduces power consumption by more than 20% with only a slight penalty in area and operating frequency. |
Identificador del proyecto | P08-TIC-03674
info:eu-repo/grantAgreement/EC/FP7/248858 TEC2010-16870/MIC |
Cita | Mora Gutiérrez, J.M., Jiménez Fernández, C.J. y Valencia Barrero, M. (2012). Low Power Implementation of Trivium Stream Cipher. En PATMOS 2012 : 22nd International Workshop on Power and Timing Modeling, Optimization and Simulation (113-120), Newcastle upon Tyne, UK: Springer. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Low Power Implementation.pdf | 228.5Kb | [PDF] | Ver/ | |