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Fault Attack on FPGA implementations of Trivium Stream Cipher

 

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Opened Access Fault Attack on FPGA implementations of Trivium Stream Cipher
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Author: Potestad Ordóñez, Francisco Eugenio
Jiménez Fernández, Carlos Jesús
Valencia Barrero, Manuel
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2016
Published in: ISCAS 2016 : IEEE International Symposium on Circuits and Systems (2016), p 562-565
ISBN/ISSN: 978-1-4799-5341-7
2379-447X
Document type: Presentation
Abstract: This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.
Cite: Potestad Ordóñez, F.E., Jiménez Fernández, C.J. y Valencia Barrero, M. (2016). Fault Attack on FPGA implementations of Trivium Stream Cipher. En ISCAS 2016 : IEEE International Symposium on Circuits and Systems (562-565), Montreal, QC, Canada: IEEE Computer Society.
Size: 206.9Kb
Format: PDF

URI: http://hdl.handle.net/11441/64960

DOI: 10.1109/ISCAS.2016.7527302

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