Ponencia
ASIC-in-the-loop methodology for verification of piecewise affine controllers
Autor/es | Martínez Rodríguez, Macarena Cristina
Brox Jiménez, Piedad Castro, Javier Tena Sánchez, Erica Acosta Jiménez, Antonio José Baturone Castillo, María Iluminada |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2012 |
Fecha de depósito | 2017-03-23 |
Publicado en |
|
ISBN/ISSN | 978-1-4673-1261-5 |
Resumen | This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. ... This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations. |
Identificador del proyecto | EC/FP7/248858
TEC2011-24319 P08-TIC-03674 |
Cita | Martínez Rodríguez, M.C., Brox Jiménez, P., Castro, J., Tena Sánchez, E., Acosta Jiménez, A.J. y Baturone Castillo, M.I. (2012). ASIC-in-the-loop methodology for verification of piecewise affine controllers. En Comunicación presentada al "19th IEEE International Conference on Electronics, Circuits and Systems" (388-391), Sevilla: Institute of Electrical and Electronics Engineers. |