Listar Ponencias (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por autor "Delgado Restituto, Manuel"
Mostrando ítems 1-20 de 38
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Ponencia
1/f/sup y/ noise generation through a chaotic nonlinear switched-capacitor circuit
(Institute of Electrical and Electronics Engineers, 1992)A programmable switched-capacitor circuit for the generation of 1/f/sup y/ noise is reported. The circuit is described by ...
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Ponencia
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
(The International Society for Optical Engineering- SPIE, 2005)This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated ...
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Ponencia
A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter
(Institute of Electrical and Electronics Engineers, 2005)This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline ...
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Ponencia
A 2.2 μW analog front-end for multichannel neural recording
(Institute of Electrical and Electronics Engineers, 2017)In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised ...
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Ponencia
A 4-mode reconfigurable low noise amplifier for implantable neural recording channels
(Institute of Electrical and Electronics Engineers, 2016)In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is ...
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Ponencia
A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology
(Institute of Electrical and Electronics Engineers, 2007)An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum ...
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Ponencia
A 64-channel inductively-powered neural recording sensor array
(Institute of Electrical and Electronics Engineers, 2012)This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, ...
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Ponencia
A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications
(Institute of Electrical and Electronics Engineers, 2016)This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical ...
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Ponencia
A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation
(Institute of Electrical and Electronics Engineers, 2017)A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS ...
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Ponencia
A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation
(Institute of Electrical and Electronics Engineers, 2019)This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation ...
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Ponencia
A low-power reconfigurable ADC for biomedical sensor interfaces
(Institute of Electrical and Electronics Engineers, 2009)This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs ...
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Ponencia
A power efficient neural spike recording channel with data bandwidth reduction
(Institute of Electrical and Electronics Engineers, 2011)This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power ...
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Ponencia
A self-calibration circuit for a neural spike recording channel
(Institute of Electrical and Electronics Engineers, 2011)This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth ...
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Ponencia
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording
(Institute of Electrical and Electronics Engineers, 2019)This paper presents a sub-μW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology ...
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Ponencia
A Sub-μVRms Chopper Front-End for ECoG Recording
(Institute of Electrical and Electronics Engineers, 2019)This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal ...
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Ponencia
An auto-calibrated neural spike recording channel with feature extraction capabilities
(The International Society for Optics and Photonics, 2011)This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration ...
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Ponencia
An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2005)This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm ...
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Ponencia
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
(Institute of Electrical and Electronics Engineers, 2019)This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends ...
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Ponencia
CMOS current-mode chaotic neurons
(Institute of Electrical and Electronics Engineers, 1994)This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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Ponencia
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
(Institute of Electrical and Electronics Engineers, 1993)This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS ...