Listar Ponencias (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por título
Mostrando ítems 41-60 de 307
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Ponencia
A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation
(Institute of Electrical and Electronics Engineers, 2019)This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation ...
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Ponencia
A low-power reconfigurable ADC for biomedical sensor interfaces
(Institute of Electrical and Electronics Engineers, 2009)This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs ...
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Ponencia
A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) ...
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Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable ...
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Ponencia
A mixed-signal fuzzy controller and its application to soft start of DC motors
(Institute of Electrical and Electronics Engineers, 2000)Presents a mixed-signal fuzzy controller chip and its application to control of DC motors. The controller is based on a ...
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Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. ...
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Ponencia
A modular CMOS analog fuzzy controller
(Institute of Electrical and Electronics Engineers, 1997)The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy ...
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Ponencia
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural ...
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Ponencia
A multiplexed mixed-signal fuzzy architecture
(Institute of Electrical and Electronics Engineers, 1998)Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. ...
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Ponencia
A new reconfigurable cascade ΣΔ modulator architecture with inter-stage resonation and no digital cancellation logic
(2009)This paper presents a new two-stage cascade ΣΔ modula- tor architecture that uses inter-stage resonation to increase its ...
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Ponencia
A novel CMOS analog neural oscillator cell
(Institute of Electrical and Electronics Engineers, 1989)A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit ...
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Ponencia
A novel low-voltage reconfigurable ΣΔ modulator for 4G wireless receivers
(2008)This paper presents a new adaptable cascade ΣΔ modulator architecture fo r low-voltage multi-stan- dard applications. ...
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Ponencia
A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the ...
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Ponencia
A piecewise-linear function approximation using current mode circuits
(Institute of Electrical and Electronics Engineers, 1992)A methodology to design currentmode circuits for piecewise-linear function approximation is presented. The technique is ...
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Ponencia
A power efficient neural spike recording channel with data bandwidth reduction
(Institute of Electrical and Electronics Engineers, 2011)This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power ...
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Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog ...
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Ponencia
A prototype node for wireless vision sensor network applications development
(Institute of Electrical and Electronics Engineers, 2010)This paper presents a prototype vision-enabled sensor node based on a commercial vision system of reduced size and power ...
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Ponencia
A prototype tool for optimum analog sizing using simulated annealing
(Institute of Electrical and Electronics Engineers, 1992)It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing ...
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Ponencia
A QCIF 145dB imager for focal plane processor chips using a tone mapping technique in standard 0.35μm CMOS technology
(2011)This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by ...
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Ponencia
A QVGA Vision Sensor with Multi-functional Pixels for Focal-Plane Programmable Obfuscation
(Institute of Electrical and Electronics Engineers, 2014)Privacy awareness constitutes a critical aspect for smart camera networks. An ideal awless protection of sensitive information ...