Listar Ponencias (Electrónica y Electromagnetismo) por autor "Valencia Barrero, Manuel"
Mostrando ítems 1-4 de 4
-
Ponencia
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007)One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation ...
-
Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ...
-
Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ...
-
Ponencia
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
(Springer, 2002)The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to ...