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- Ponencias (Electrónica y Electromagnetismo)
- Listar Ponencias (Electrónica y Electromagnetismo) por autor
Listar Ponencias (Electrónica y Electromagnetismo) por autor "Acosta Jiménez, Antonio José"
Mostrando ítems 1-7 de 7
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Ponencia
ASIC-in-the-loop methodology for verification of piecewise affine controllers
Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Castro, Javier; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2012)This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable ...
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Ponencia
Asymmetric clock driver for improved power and noise performances
Castro, Javier; Parra Fernández, María del Pilar; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José (IEEE Computer Society, 2007)One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation ...
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Ponencia
Automated experimental setup for EM cartography to enhance EM attacks
Tena Sánchez, Erica; Casado Galán, Alejandro; Zúñiga González, Virginia; Potestad Ordóñez, Francisco Eugenio; Acosta Jiménez, Antonio José (2022)Side-channel attacks are a real threat, exploiting and revealing the secret data stored in our electronic devices ...
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Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ...
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Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ...
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Ponencia
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
Parra Fernández, María del Pilar; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2002)The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to ...
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Ponencia
Using physical unclonable functions for hardware authentication: a survey
Eiroa, Susana; Baturone Castillo, María Iluminada; Acosta Jiménez, Antonio José; Dávila, Jorge (2010)Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special ...