A 20Mevps/32Mev event-based USB framework for neuromorphic systems debugging

Abstract

Neuromorphic systems are engineering solutions that take inspiration from biological neural systems. They use spike-or event-based representation and codification of the information. This codification allows performing complex computations, filters, classifications and learning in a pseudo-simultaneous way. Small incremental processing is done per event, which shows useful results with very low latencies. Therefore, developing this kind of systems requires the use of specialized tools for debugging and testing those flows of events. This paper presents a set of logic implementations for FPGA that assists on the development of event-based systems and their debugging. Address-Event-Representation (AER) is a communication protocol for transferring events/spikes between bio-inspired chips/systems. Real-time monitoring and sequencing, logging and playing back long sequences of events/spikes to and from memory; and several merging and splitting ports are the main requirements when developing these systems. These functionalities and implementations are explained and tested in this work. The logic has been evaluated in an Opal-Kelly XEM6010 acting as a daughter board for the AER-Node platform. It has a peak rate of 20Mevps when logging and a total of 32Mev of logging capacity on DDR when debugging an AER system in the AER-Node or a set of them connected in daisy chain.