dc.creator | Rivas Pérez, Manuel | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Gómez Rodríguez, Francisco de Asís | es |
dc.creator | Morgado Estévez, Arturo | es |
dc.creator | Civit Balcells, Antón | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.date.accessioned | 2019-12-16T09:41:06Z | |
dc.date.available | 2019-12-16T09:41:06Z | |
dc.date.issued | 2011 | |
dc.identifier.citation | Rivas Pérez, M., Linares Barranco, A., Gómez Rodríguez, F.d.A., Morgado, A., Civit Balcells, A. y Jiménez Moreno, G. (2011). An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata. En IWANN 2011: 11th International Work-Conference on Artificial Neural Networks (157-165), Torremolinos, Málaga: Springer. | |
dc.identifier.isbn | 978-3-642-21500-1 | es |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | https://hdl.handle.net/11441/90928 | |
dc.description.abstract | Spike-based systems are neuro-inspired circuits implementations
traditionally used for sensory systems or sensor signal processing. Address-Event-
Representation (AER) is a neuromorphic communication protocol for transferring
asynchronous events between VLSI spike-based chips. These neuro-inspired
implementations allow developing complex, multilayer, multichip neuromorphic
systems and have been used to design sensor chips, such as retinas and cochlea,
processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata
(CA) is a bio-inspired processing model for problem solving. This approach
divides the processing synchronous cells which change their states at the same time
in order to get the solution. This paper presents a software simulator able to gather
several spike-based elements into the same workspace in order to test a CA
architecture based on AER before a hardware implementation. Furthermore this
simulator produces VHDL for testing the AER-CA into the FPGA of the USBAER
AER-tool. | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2009-10639-C04-02 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | IWANN 2011: 11th International Work-Conference on Artificial Neural Networks (2011), p 157-165 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Spiking neurons | es |
dc.subject | Address-event-representation | es |
dc.subject | Usb-aer | es |
dc.subject | VHDL | es |
dc.subject | FPGA | es |
dc.subject | Image filtering | es |
dc.subject | Neuro-inspired | es |
dc.subject | Cellular automata | es |
dc.title | An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | TEC2009-10639-C04-02 | es |
dc.relation.publisherversion | https://link.springer.com/chapter/10.1007/978-3-642-21501-8_20 | es |
dc.identifier.doi | 10.1007/978-3-642-21501-8_20 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | |
idus.format.extent | 9 | es |
dc.publication.initialPage | 157 | es |
dc.publication.endPage | 165 | es |
dc.eventtitle | IWANN 2011: 11th International Work-Conference on Artificial Neural Networks | es |
dc.eventinstitution | Torremolinos, Málaga | es |
dc.relation.publicationplace | Berlin | es |
dc.identifier.sisius | 6538104 | es |