Artículo
Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
Autor/es | Ginés Arteaga, Antonio José
Peralías Macías, Eduardo Léger, Gildas Rueda Rueda, Adoración |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2014 |
Fecha de depósito | 2018-05-10 |
Publicado en |
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Resumen | This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to ... This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity. |
Agencias financiadoras | Junta de Andalucía Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | P09-TIC-5386
TEC2011-28302 |
Cita | Ginés Arteaga, A.J., Peralías Macías, E., Leger Leger, G. y Rueda Rueda, A. (2014). Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators. IEEE International Conference on Electronics, Circuits and Systems (ICCES), 538-541. |
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Closed-loop Simulation Method.pdf | 308.6Kb | [PDF] | Ver/ | |