dc.creator | Ginés Arteaga, Antonio José | es |
dc.creator | Peralías Macías, Eduardo | es |
dc.creator | Léger, Gildas | es |
dc.creator | Rueda Rueda, Adoración | es |
dc.date.accessioned | 2018-05-10T13:42:38Z | |
dc.date.available | 2018-05-10T13:42:38Z | |
dc.date.issued | 2014 | |
dc.identifier.citation | Ginés Arteaga, A.J., Peralías Macías, E., Leger Leger, G. y Rueda Rueda, A. (2014). Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators. IEEE International Conference on Electronics, Circuits and Systems (ICCES), 538-541. | |
dc.identifier.uri | https://hdl.handle.net/11441/74450 | |
dc.description.abstract | This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity. | es |
dc.description.sponsorship | Junta de Andalucía P09-TIC-5386 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2011-28302 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE International Conference on Electronics, Circuits and Systems (ICCES), 538-541. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Comparator offset evaluation | es |
dc.subject | Discrete-time | es |
dc.subject | Flash- ADC | es |
dc.subject | Simulation-based techniques | es |
dc.title | Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators | es |
dc.type | info:eu-repo/semantics/article | es |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | P09-TIC-5386 | es |
dc.relation.projectID | TEC2011-28302 | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/ICECS.2014.7050041 | es |
dc.identifier.doi | 10.1109/ICECS.2014.7050041 | es |
idus.format.extent | 4 p. | es |
dc.journaltitle | IEEE International Conference on Electronics, Circuits and Systems (ICCES) | es |
dc.publication.initialPage | 538 | es |
dc.publication.endPage | 541 | es |
dc.contributor.funder | Junta de Andalucía | |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | |