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Complementary tunnel gate topology to reduce crosstalk effects
dc.creator | Núñez Martínez, Juan | es |
dc.creator | Avedillo de Juan, María José | es |
dc.date.accessioned | 2018-05-03T14:31:02Z | |
dc.date.available | 2018-05-03T14:31:02Z | |
dc.date.issued | 2017 | |
dc.identifier.citation | Nuñez Martínez, J. y Avedillo de Juan, M.J. (2017). Complementary tunnel gate topology to reduce crosstalk effects. En Design of Circuits and Integrated Systems (DCIS) (1-5), Granada, 23-25 November 2016: Institute of Electrical and Electronics Engineers (IEEE). | |
dc.identifier.uri | https://hdl.handle.net/11441/73989 | |
dc.description.abstract | Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es |
dc.relation.ispartof | Design of Circuits and Integrated Systems (DCIS) (2017), pp. 1-5. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Tunnel transistors | es |
dc.subject | Steep subthreshold slope | es |
dc.subject | Noise coupling | es |
dc.subject | Low power | es |
dc.subject | Energy efficieny | es |
dc.subject | Low supply voltage | es |
dc.title | Complementary tunnel gate topology to reduce crosstalk effects | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | https://doi.org/10.1109/DCIS.2016.7845264 | es |
dc.identifier.doi | 10.1109/DCIS.2016.7845264 | es |
idus.format.extent | 5 p. | es |
dc.publication.initialPage | 1 | es |
dc.publication.endPage | 5 | es |
dc.eventtitle | Design of Circuits and Integrated Systems (DCIS) | es |
dc.eventinstitution | Granada, 23-25 November 2016 | es |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Complementary Tunnel.pdf | 110.5Kb | [PDF] | Ver/ | |