Ponencia
High-order cascade multi-bit Σ∆ modulators for high-speed A/D conversion
Autor/es | Río Fernández, Rocío del
Medeiro Hidalgo, Fernando Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1998 |
Fecha de depósito | 2016-01-22 |
Publicado en |
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ISBN/ISSN | 8460683457 |
Resumen | The use of Sigma-Delta (Σ∆) modulation
for analog-to-digital conversion (ADC) in the
communication frequency range is evaluated. Two
high-order multi-bit architectures are proposed to
achieve +12-bit dynamic range at ... The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Higher_order_cascade.pdf | 4.300Mb | [PDF] | Ver/ | |