dc.creator | Millán Calderón, Alejandro | |
dc.creator | Juan Chico, Jorge | |
dc.creator | Bellido Díaz, Manuel Jesús | |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | |
dc.creator | Guerrero Martos, David | |
dc.creator | Ostúa Arangüena, Enrique | |
dc.date.accessioned | 2015-11-30T08:38:23Z | |
dc.date.available | 2015-11-30T08:38:23Z | |
dc.date.issued | 2004 | |
dc.identifier.citation | Millán Calderón, A., Juan Chico, J., Bellido Díaz, M.J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D. y Ostúa Arangüena, E. (2004). Signal Sampling Based Transition Modeling for Digital Gates Characterization. Lecture Notes in Computer Science, 3254, 829-837. | |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | http://hdl.handle.net/11441/31227 | |
dc.description | Es una ponencia del Congreso: PATMOS 2004 : 14th International Workshop on Power and Timing Modeling, Optimization and Simulation. ISBN: 978-3-540-23095-3 | |
dc.description.abstract | Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%. | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología VERDI TIC 2002-2283 | es |
dc.description.sponsorship | Ministerio de Educación, Cultura y Deporte / Secretaría de Estado de Educación y Universidades / Dirección General de Universidades PHB2002-0018-PC | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | Lecture Notes in Computer Science, 3254, 829-837. | |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Digital circuit | es |
dc.subject | CMOS | es |
dc.subject | Characterization | es |
dc.subject | Logic simulation | es |
dc.title | Signal Sampling Based Transition Modeling for Digital Gates Characterization | es |
dc.type | info:eu-repo/semantics/article | es |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | VERDI TIC 2002-2283 | es |
dc.relation.projectID | PHB2002-0018-PC | es |
dc.relation.publisherversion | http://dx.doi.org/10.1007/978-3-540-30205-6_85 | es |
dc.identifier.doi | 10.1007/978-3-540-30205-6_85 | es |
dc.journaltitle | Lecture Notes in Computer Science | es |
dc.publication.volumen | 3254 | es |
dc.publication.initialPage | 829 | es |
dc.publication.endPage | 837 | es |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/31227 | |
dc.contributor.funder | Ministerio de Ciencia y Tecnología (MCYT). España | |
dc.contributor.funder | Ministerio de Educación, Cultura y Deporte (MECD). España | |