Article
Signal Sampling Based Transition Modeling for Digital Gates Characterization
Author/s | Millán Calderón, Alejandro
Juan Chico, Jorge Bellido Díaz, Manuel Jesús Ruiz de Clavijo Vázquez, Paulino Guerrero Martos, David Ostúa Arangüena, Enrique |
Department | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Publication Date | 2004 |
Deposit Date | 2015-11-30 |
Published in |
|
Abstract | Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. ... Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%. |
Funding agencies | Ministerio de Ciencia y Tecnología (MCYT). España Ministerio de Educación, Cultura y Deporte (MECD). España |
Project ID. | VERDI TIC 2002-2283
PHB2002-0018-PC |
Citation | Millán Calderón, A., Juan Chico, J., Bellido Díaz, M.J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D. y Ostúa Arangüena, E. (2004). Signal Sampling Based Transition Modeling for Digital Gates Characterization. Lecture Notes in Computer Science, 3254, 829-837. |
Files | Size | Format | View | Description |
---|---|---|---|---|
LNCS 2004 post-print.pdf | 140.9Kb | [PDF] | View/ | |