Artículo
A High-voltage Floating Level Shifter for a Multi-stage Charge-pump in a Standard 1.8 V/3.3 V CMOS Process
Autor/es | Palomeque Mangut, David
Rodríguez Vázquez, Ángel Benito Delgado Restituto, Manuel |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2022 |
Fecha de depósito | 2024-07-30 |
Publicado en |
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Resumen | This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from ... This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA. |
Cita | Palomeque Mangut, D., Rodríguez Vázquez, Á.B. y Delgado Restituto, M. (2022). A High-voltage Floating Level Shifter for a Multi-stage Charge-pump in a Standard 1.8 V/3.3 V CMOS Process. AEU - International Journal of Electronics and Communications, 156, 154389. https://doi.org/10.1016/j.aeue.2022.154389. |
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