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A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation
dc.creator | Asghar, Sohail | es |
dc.creator | Afridi, Sohaib Saadat | es |
dc.creator | Pillai, Anu | es |
dc.creator | Schuler, Anita | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.creator | O'Connell, Ivan | es |
dc.date.accessioned | 2023-12-18T12:57:52Z | |
dc.date.available | 2023-12-18T12:57:52Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Asghar, S., Afridi, S.S., Pillai, A., Schuler, A., Rosa Utrera, J.M.d.l. y O'Connell, I. (2018). A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation. IEEE Transactions on Circuits and Systems I: Regular Papers, 65 (11), 8439041. https://doi.org/10.1109/TCSI.2018.2852761. | |
dc.identifier.issn | 1549-8328 | es |
dc.identifier.issn | 1558-0806 | es |
dc.identifier.uri | https://hdl.handle.net/11441/152637 | |
dc.description.abstract | Abstract— A 12-bit successive approximation register analogto-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 Vpp−d (±1.33 VREF). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-µm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/−1.0 LSB and INL of 2.3/−2.2 LSB. | es |
dc.format | application/pdf | es |
dc.format.extent | 11 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I: Regular Papers, 65 (11), 8439041. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.subject | SAR | es |
dc.subject | comparator offset | es |
dc.subject | capacitor segmentation | es |
dc.subject | feedback control system | es |
dc.title | A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | https://dx.doi.org/10.1109/TCSI.2018.2852761 | es |
dc.identifier.doi | 10.1109/TCSI.2018.2852761 | es |
dc.journaltitle | IEEE Transactions on Circuits and Systems I: Regular Papers | es |
dc.publication.volumen | 65 | es |
dc.publication.issue | 11 | es |
dc.publication.initialPage | 8439041 | es |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Asgh18_postprint.pdf | 2.579Mb | ![]() | Ver/ | Versión aceptada |
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