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Mostrando ítems 31-40 de 131
Ponencia
Sistemas de Gestión Logística: Modelo de Gestión y Proceso de Auditoría
(Asociación para el Desarrollo de la Ingeniería de Organización (ADINGOR), 2006)
El proyecto presentado surge de la identificación de la logística como un factor crucial para las empresas, constituyendo una verdadera ventaja para la competitividad para las mismas, no sólo por su repercusión en la ...
Ponencia
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an ...
Ponencia
Ponencia
Efficient Design of a FFT/IFFT-64 Module on ASIC
(IBERCHIP, 2005)
In this work we present the VHDL implementation of a FFT/IFFT-64 module. This implementation: (a) is relatively quick and (b) occupies a limited amount of area. The module operation is based on a radix-8 butterfly and ...
Ponencia
Aprendizaje de flujos de diseño comerciales durante práticas en empresa
(Universidad Politécnica de Madrid, 2002)
En esta comunicación se detalla el aprendizaje de distintas herramientas comerciales de diseño de circuitos digitales en el marco de la realización de prácticas en empresa. Este aprendizaje se centra en el empleo de ...
Ponencia
Using laboratory to improve understanding of 802.3 physical characteristics
(IEEE Computer Society, 2009)
When teaching computer networks as part of a Computer Engineering degree, emphasis is placed on higher-layer protocols while Physical and Data-Link layers usually play a secondary role. Physical aspects of data ...
Ponencia
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements
(IEEE Computer Society, 2006)
This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network ...
Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
Ponencia
Giving Neurons to Sensors: An Approach to QoS Management Through Artificial Intelligence in Wireless Networks
(Springer, 2006)
For the latest ten years, many authors have focused their investigations in wireless sensor networks. Different researching issues have been extensively developed: power consumption, MAC protocols, selforganizing network ...
Ponencia
Choosing the Right Protocol Stack for an Open and Flexible Remote Unit
(IEEE Computer Society, 2008)
This paper presents some works made in the development of communications software for an embedded open core system. By using a Linux-based processor implemented on a FPGA, we are developing the appropriate software in ...