Buscar
Mostrando ítems 11-20 de 49
Ponencia
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ...
Ponencia
Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks
(Universitat Politécnica de Catalunya, 2016)
Ponencia
Realización de prácticas de electrónica digital con un esquema de documentación jerarquizada
(Universidad Politécnica de Valencia, 2004)
En esta comunicación se presenta la realización de una actividad teórico-práctica, encuadrada dentro del marco ECTS, para un primer curso de Electrónica Digital. Está ideada para desarrollarse en un entorno de bajo coste ...
Ponencia
Creating helping posters for electronic labs
(IEEE Computer Society, 2016)
A Project is presented whose aim was to develop a set of posters that, as small tutorials, shows in a very visual way what are the basic task to do in a laboratory of electronic. These posters are directed to students ...
Ponencia
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an ...
Ponencia
Realización de un Sistema Digital: implementación sobre FPGA y testado en Laboratorio
(Universidad Politécnica de Madrid, 1998)
Ponencia
High Radix Implementation of Montgomery Multipliers with CSA
(IEEE Computer Society, 2010)
Modular multiplication is the key operation in systems based on public key encryption, both for RSA and elliptic curve (ECC) systems. High performance hardware implementations of RSA and ECC systems use the Montgomery ...
Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
Ponencia
Educational applications of a pico-processor design
(IEEE Computer Society, 2016)
Knowledge of the internal structure and operating mechanism of microprocessors is a very important part in for engineers in electronics and computer science. This knowledge can be deepened with experiences of processor ...
Ponencia
Diseño de circuitos integrados y seguridad de circuitos criptográficos frente a ataques
(Área de Innovación y Desarrollo, 2016)
Muchos sistemas electrónicos incorporan dispositivos criptográficos que implementan algoritmos que cifran la información almacenada. Pero aun cuando los algoritmos sean muy seguros, estos dispositivos pueden llegar a revelar ...