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Ponencia
Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión
(Universidad de Alcalá, 2009)
Este trabajo presenta el diseño y la implementación sobre FPGA de un cliente SNTP compacto, de bajo coste y alta precisión, específico para entornos IEC 61850. Este módulo cliente es capaz de sincronizarse con un servidor ...
Ponencia
A SoC Design Methodology for LEON2 on FPGA
(IBERCHIP, 2006)
SoC design methodologies show up as a natural and productive method to implement embedded and/or ubiquitous systems. The authors explore the possibilities of the free LEON2 processor core, originally developed by the ...
Ponencia
Metodología PBL en modo colaborativo aplicada al diseño de un SoC
(Universidad de Sevilla, 2016)
Dado el carácter principalmente práctico en las asignaturas de los másteres universitarios la metodología PBL es ampliamente utilizada. Este trabajo presenta una experiencia docente de varios años, donde se aplica PBL, ...
Ponencia
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
(IEEE Computer Society, 2001)
As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which is necessary to face in order to achieve a practical i ...
Ponencia
Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de electrónica.
(Universidad Politécnica de Valencia, 2004)
En este trabajo se propone una práctica de laboratorio para la asignatura Estructura de Computadores de primer curso de Ingeniería Informática consistente en el análisis de una videoconsola. El objetivo básico consiste ...
Ponencia
Virtualization environment for IT labs development and assessment
(IEE Xplore, 2022)
In this contribution, the advantages of using a virtualization platform for IT laboratories is demonstrated. The platform used is based on free (open-source) software and present important advantages with respect to previous ...
Ponencia
Application of virtualization technology to the study of quality of service techniques
(IEEE Computer Society, 2014)
In this article, the teaching of quality of service mechanisms in packet-switched networks is presented. To this end, a methodology based on virtualization technology is introduced. As a result, a truly practical approach ...
Ponencia
Internode: Internal Node Logic Computational Model
(IEEE Computer Society, 2003)
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal ...
Ponencia
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ...
Ponencia
A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot
(IEEE Computer Society, 2018)
Nowadays, honeypots are a key tool to attract attackers and study their activity. They help us in the tasks of evaluating attacker's behaviour, discovering new types of attacks, and collecting information and statistics ...