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Listar Artículos (Tecnología Electrónica) por autor "Juan Chico, Jorge"
Mostrando ítems 1-15 de 15
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Address encoded byte order
Guerrero Martos, David; Cano Quiveu, Germán; Juan Chico, Jorge; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Viejo Cortés, Julián; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique (Elsevier B.V., 2020)Unaligned accesses are forbidden in many high-performance architectures. In most of these architectures, the least ...
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An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation
Cano Quiveu, Germán; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Viejo Cortés, Julián; Juan Chico, Jorge (IEEE Computer Society, 2021)This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the ...
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Analysis of Metastable Operation in a CMOS Dynamic D-Latch
Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel; Huertas Díaz, José Luis (Springer, 1997)Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high ...
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Application of Internode model to global power consumption estimation in SCMOS gates
Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based ...
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Automated performance evaluation of skew-tolerant clocking schemes
Guerrero Martos, David; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Taylor and Francis Online, 2006)In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes ...
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Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (Springer, 2002-08-27)In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which ...
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Embedded LUKS (E-LUKS): A Hardware Solution to IoT Security
Cano Quiveu, Germán; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Viejo Cortés, Julián; Guerrero Martos, David; Ostúa Arangüena, Enrique (MDPI, 2021)The Internet of Things (IoT) security is one of the most important issues developers have to face. Data tampering must ...
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Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
Viejo Cortés, Julián; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino (IEEE Computer Society, 2011)Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most ...
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High-Performance Time Server Core for FPGA System-on-Chip
Viejo Cortés, Julián; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Cano Quiveu, Germán (MDPI, 2019)This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server ...
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IRIS: An embedded secure boot for IoT devices
Cano Quiveu, Germán; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Viejo Cortés, Julián (Elsevier, 2023-10)This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for ...
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Long-term on-chip verification of systems with logical events scattered in time
Viejo Cortés, Julián; Villar de Ossorno, José Ignacio; Juan Chico, Jorge; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Quirós Carmona, Juan (Elsevier, 2012)Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification ...
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Minimalistic SDHC-SPI hardware reader module for boot loader applications
Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Viejo Cortés, Julián; Guerrero Martos, David (Elsevier, 2017)This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. ...
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NanoFS: a hardware-oriented file system
Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Viejo Cortés, Julián; Guerrero Martos, David (IEEE Computer Society, 2013)NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to ...
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Signal Sampling Based Transition Modeling for Digital Gates Characterization
Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique (Springer, 2004)Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel ...
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Using the complement of the cosine to compute trigonometric functions
Guerrero Martos, David; Millán Calderón, Alejandro; Juan Chico, Jorge; Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique (Springer, 2020)The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors ...