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Ponencia
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A methodological proposal for the Digital Electronics subject laboratory
(IEE Xplore, 2022)
This paper describes a proposal for teaching the digital electronics laboratory that combines the traditional method based on the assembly of discrete components on test boards with remote teaching using the virtual teaching ...
Ponencia
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Ejemplo de diseño FPGA para medidas de máximas frecuencias de operación
(Universidad de La Laguna, 2018)
La mejor forma de aprender a diseñar sistemas digitales a nivel RT es haciendo uso de ejemplos prácticos. Además, desde el punto de vista docente, cuanto más prácticos, más atractivos son para los alumnos. Pero para que ...
Ponencia
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Medición de distancias como ejemplo práctico de diseño en FPGAs
(Universidad de La Laguna, 2018)
El aprendizaje de diseño digital a nivel RT requiere de ejemplos prácticos y conforme se avanza en el aprendizaje se precisa que los ejemplos aumenten de complejidad. Las FPGA y las placas de desarrollo ofrecen una plataforma ...
Capítulo de Libro
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Network Time Synchronization: A Full Hardware Approach
(Springer, 2012)
Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system and software application. Each abstraction level greatly facilitates the design task at the cost ...
Ponencia
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A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
(Institute of Electrical and Electronics Engineers, 2023-12)
As the AES is the standard symmetric cipher selected by NIST, is the best-known and the most widely used block cipher. Consequently, security threats are constantly rising and increasingly powerful. With the addition of ...
Ponencia
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Learning VHDL through teamwork FPGA game design
(IEEE Computer Society, 2020)
The learning of digital design at the RT level by the students improves with practical work, which can be developed in teams, allow both the gradual advance of complexity as the learning progresses, and the proposal to ...
Ponencia
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Maximum Operating Frequency Self-Tuning System on FPGAs Using Dynamic Reconfiguration
(2023-12)
This paper proposes the use of a dynamic clock frequency reconfiguration technique to optimize the performance of a circuit by changing its clock frequency to achieve the maximum operating frequency. The proposed technique ...
Ponencia
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evercodeML: a formal language for SoC integration
(IEEE Computer Society, 2015)
Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like ...
Ponencia
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Building a basic membrane computer
(Fénix, 2016)
In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel ...
Ponencia
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Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
(IEEE Computer Society, 2018)
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based ...