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Mostrando ítems 261-270 de 301
Ponencia
AER Auditory Filtering and CPG for Robot Control
(IEEE Computer Society, 2007)
Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). The ...
Ponencia
ED-Scorbot: A Robotic test-bed Framework for FPGA-based Neuromorphic systems
(IEEE Computer Society, 2016)
Neuromorphic engineering is a growing and promising discipline nowadays. Neuro-inspiration and brain understanding applied to solve engineering problems is boosting new architectures, solutions and products today. The ...
Ponencia
Labeling Color 2D Digital Images in Theoretical Near Logarithmic Time
(Springer, 2017)
A design of a parallel algorithm for labeling color flat zones (precisely, 4-connected components) of a gray-level or color 2D digital image is given. The technique is based in the construction of a particular Homological ...
Ponencia
EdgeDRNN: Enabling Low-latency Recurrent Neural Network Edge Inference
(IEEE Xplore, 2020-09)
This paper presents a Gated Recurrent Unit (GRU) based recurrent neural network (RNN) accelerator called Edge-DRNN designed for portable edge computing. EdgeDRNN adopts the spiking neural network inspired delta network ...
Ponencia
A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion
(IEEE Computer Society, 2004)
A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS ...
Ponencia
Foveal-pit inspired filtering of DVS spike response
(Institute of Electrical and Electronics Engineers Inc. (IEEE), 2021)
In this paper, we present results of processing Dynamic Vision Sensor (DVS) recordings of visual patterns with a retinal model based on foveal-pit inspired Difference of Gaussian (DoG) filters. A DVS sensor was stimulated ...
Ponencia
Análisis a Bajo Nivel de Procesadores Superescalares Reales
(Universidad de Alcalá de Henares. Servicio de Publicaciones, 2000)
En esta ponencia-demo se presenta una práctica donde se analiza la influencia en el tiempo de ejecución de algunas optimizaciones sobre el código máquina para procesadores reales (familia Intel Pentium). Se propone el ...
Ponencia
Network requirements evaluation of a multi-user virtual environment
(IEEE Computer Society, 2011)
In this paper, the network traffic requirements of a virtual world based on Wonderland are studied. Object synchronization and voice traffic are studied and several experimental measures are made in order to obtain an ...
Ponencia
Desde CoOs hasta .NetFramework: Comunicación hardware/software mediante VCP
(Asociación de Enseñantes Universitarios de la Informática (AENUI), 2014)
En este artículo se describe una práctica de labora torio para la docencia de sistemas operativos en tiempo real (RTOS) para microcontroladores de 32bits en el ámbito de los grados en Ingeniería de Computadores, ...
Ponencia
LVDS Serial AER Link performance
(IEEE Computer Society, 2007)
Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems ...