Ponencia
A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion
Autor/es | Serrano Gotarredona, María Teresa
Linares Barranco, Bernabé Velarde Ramírez, Jesús |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2004 |
Fecha de depósito | 2020-09-30 |
Publicado en |
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ISBN/ISSN | 0-7803-8251-X |
Resumen | A five parameter mismatch model continuos from
weak to strong inversion is presented. The model is an
extension of a previously reported one valid in the strong
inversion region [1]. A mismatch characterization of
NMOS ... A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able to predict current mismatch with a mean relative error of 13.5% in the weak inversion region and 5% in strong inversion. This is verified for 12 different curves, sweeping , and . Since data is available for 30 different sizes, the mismatch model can be expressed as function of transistor width W and L, independently. The proposed model, with explicit W and L dependency has been implemented in the Spectre simulator. Simulations reveal that such precise modeling of mismatch (with explicit W and L dependency) can improve analog circuit performance without penalty on power and area consumption: just by splitting transistors into the optimum number of segments. |
Agencias financiadoras | Ministerio de Ciencia y Tecnología (MCYT). España Ministerio de Ciencia y Tecnología (MCYT). España Ministerio de Ciencia y Tecnología (MCYT). España Ministerio de Ciencia y Tecnología (MCYT). España Ministerio de Ciencia y Tecnología (MCYT). España European Union (UE) |
Identificador del proyecto | TIC1999-0446-C02-02
TIC2000-0406-P4-05 FIT-07000/2002/921 TIC2002-10878-E TIC-2003-08164-C03-01 IST-2001-34124 (CAVIAR) |
Cita | Serrano Gotarredona, M.T., Linares Barranco, B. y Velarde Ramírez, J. (2004). A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion. En ISCAS 2004: IEEE International Symposium on Circuits and Systems (753-756), Vancouver, BC, Canada: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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A precise CMOS mismatch model.pdf | 3.336Mb | [PDF] | Ver/ | |