Browsing Instituto de Microelectrónica de Sevilla (IMSE-CNM) by Funding agency "Comisión Interministerial de Ciencia y Tecnología (CICYT). España"
Now showing items 1-17 of 17
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Article
1 V CMOS subthreshold log domain PDM
(Springer, 2003)A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage ...
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Presentation
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
(2000)This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low ...
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Article
A CMOS 0.8- µm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion
(Institute of Electrical and Electronics Engineers, 2000)This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ modulator ...
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Article
A modular programmable CMOS analog fuzzy controller chip
(Institute of Electrical and Electronics Engineers, 1999)We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital progranirnability. This ...
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Article
Analysis of error mechanisms in switched-current Sigma-Delta modulators
(Springer, 2004)This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance ...
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Article
Efficient realization of a threshold voter for self-purging redundancy
(Springer, 2001)The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ...
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Presentation
Harmonic Distortion in Fully-Differential Switched-Current Sigma-Delta Modulators
(1999)This paper presents a systematic analysis of the harmonic distortion in SD modulators (SDMs) implemented with ...
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Presentation
Herramientas de CAD para la síntesis de sistemas de interferencia difusos mediante FPGAs
(2002)En esta comunicación se describe un flujo de diseño que permite automatizar el proceso de síntesis sobre FPGAs de sistemas ...
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Article
Low-voltage CMOS log-companding techniques for audio applications
(Springer, 2004)This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down ...
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Presentation
Mixed-signal map-configurable integrated chaos generator for digital communication systems
(2001)In this paper, the methodological aspects for the design of mixed-signal map-configurable chaos generators are presented. ...
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Article
Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors
(Institute of Electrical and Electronics Engineers, 1998)This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture ...
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Article
Multiplexing architecture for mixed-signal CMOS fuzzy controllers
(Institute of Electrical and Electronics Engineers, 1998)Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually ...
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Article
nu MOS-based sorter for arithmetic applications
(Hindawi Publishing Corporation, 2000)The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some ...
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Presentation
Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design
(1999)This paper presents a detailed study on the transient response of SC integrators taking into account the effects of ...
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Presentation
Selection of test techniques for high-resolution ΣΔ modulators
(2000)This paper introduces a new tool which allows the evaluation of different test techniques in a complete impartial manner. ...
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Article
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ...
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Article
Sorting networks implemented as νMOS circuits
(Institute of Electrical and Electronics Engineers, 1998)A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.