Article
1 V CMOS subthreshold log domain PDM
| Author/s | Serra Graells, Francesc
Huertas Díaz, José Luis |
| Date | 2003 |
| Published in |
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| Abstract | A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing ... |
| Funding agencies | Comisión Interministerial de Ciencia y Tecnología (CICYT). España European Union (UE) |
| Project ID. | TIC97-1159
TIC99-1084
23068 |
| Citation | Serra Graells, F. y Huertas Díaz, J.L. (2003). 1 V CMOS subthreshold log domain PDM. Analog Integrated Circuits and Signal Processing, 34 (3), 183-187. |
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| Files | Size | Format | View | Description |
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| 1V CMOS Subthreshold.pdf | 277.4Kb | 
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https://hdl.handle.net/11441/77207
https://doi.org/10.1023/A:1022545414777This item appears in the following collection(s)
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