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A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration [Presentation]
(Institute of Electrical and Electronics Engineers, 2014)
his paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which ...

A modulator/demodulator CMOS IC for chaotic encryption of audio [Presentation]
(Institute of Electrical and Electronics Engineers, 1995)
This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. It is based on a gm-Cmodu¬ lator/demodulator analog CMOS IC that implements a 3rd-order nonlinear ...

Symbolic analysis of large analog integrated circuits: the numerical reference generation problem [Chapter of Book]
(IEEE press, 1998)
Symbolic analysis potentialities for gaining circuit insight and for efficient repetitive evaluations have been limited by the exponential increase of formula complexity with the circuit size. This drawback has began to ...

A FPP-oriented tone mapping technique for high dynamic range imagers using temporal and final exposure measurements [Presentation]
(Institute of Electrical and Electronics Engineers, 2010)
This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors due to its very limited computing requirements since only local memories and a comparator ...

Focal-plane sensing-processing: a power-efficient approach for the implementation of privacy-aware networked visual sensors [Article]
(MDPI, 2014)
The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image ...

VISCUBE: A multi-layer vision chip [Chapter of Book]
(Springer Science+Business Media, 2011)
Vertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital processor arrays on a four layer structure is introduced. The mixed-signal processor array is designed ...

Electrooptical measurement system for the DC characterization of visible detectors for CMOS-compatible vision chips [Article]
(IEEE, 1998)
Abstract—An electrooptical measurement system for the dc characterization of visible detectors for CMOS-compatible vision chips is presented, which can help designers to characterize these detectors. The measurement ...

A mixed-signal architecture for high complexity CMOS fuzzy controlers [Article]
(Universidad de Granada: Departamento de Ciencias de la Computación e Inteligencia Artificial, 1999)
Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements [1]. This limit in precision, as well as the lack of design tools when compared to the digital ...

Redes neuronales celulares: modelado y diseño monolítico [PhD Thesis]
(1994-03-21)
Las aportaciones principales de esta Tesis se refieren al diseño de circuitos electrónicos con las primitivas disponibles en tecnologías CMOS standard, y a la integración monolítica de los mismos en chips de altas y muy-altas ...