Artículo
Trivium hardware implementations for power reduction
Autor/es | Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2017 |
Fecha de depósito | 2021-03-15 |
Publicado en |
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Resumen | This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware
implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a
combination of ... This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | TEC2010-16870
TEC2013-45523-R CSIC 201550E039 |
Cita | Mora Gutiérrez, J.M., Jiménez Fernández, C.J. y Valencia Barrero, M. (2017). Trivium hardware implementations for power reduction. International Journal of Circuit Theory and Applications, 45 (2), 188-198. |
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