dc.creator | Mora Gutiérrez, José Miguel | es |
dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2021-03-15T12:08:10Z | |
dc.date.available | 2021-03-15T12:08:10Z | |
dc.date.issued | 2017 | |
dc.identifier.citation | Mora Gutiérrez, J.M., Jiménez Fernández, C.J. y Valencia Barrero, M. (2017). Trivium hardware implementations for power reduction. International Journal of Circuit Theory and Applications, 45 (2), 188-198. | |
dc.identifier.issn | 0098-9886 | es |
dc.identifier.uri | https://hdl.handle.net/11441/106054 | |
dc.description.abstract | This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware
implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a
combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware
profile of the eSTREAM project. So that their power consumption values can be compared and verified, the
proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology
with both transistors and gate-level models, in order to permit both electrical and logical simulations.
The results show that the two designs decreased average power consumption by between 15% and 25% with
virtually no performance loss and only a slight overhead (about 5%) in area. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2010-16870 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-45523-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad CSIC 201550E039 | es |
dc.format | application/pdf | es |
dc.format.extent | 11 | es |
dc.language.iso | eng | es |
dc.publisher | Wiley | es |
dc.relation.ispartof | International Journal of Circuit Theory and Applications, 45 (2), 188-198. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Trivium | es |
dc.subject | Stream Cipher | es |
dc.subject | Low-power | es |
dc.subject | lightweight cryptography | es |
dc.subject | Hardware implementations | es |
dc.title | Trivium hardware implementations for power reduction | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2010-16870 | es |
dc.relation.projectID | TEC2013-45523-R | es |
dc.relation.projectID | CSIC 201550E039 | es |
dc.relation.publisherversion | https://onlinelibrary.wiley.com/doi/full/10.1002/cta.2281 | es |
dc.identifier.doi | 10.1002/cta.2281 | es |
dc.journaltitle | International Journal of Circuit Theory and Applications | es |
dc.publication.volumen | 45 | es |
dc.publication.issue | 2 | es |
dc.publication.initialPage | 188 | es |
dc.publication.endPage | 198 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |