Artículo
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium
Autor/es | Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2020 |
Fecha de depósito | 2021-03-15 |
Publicado en |
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Resumen | We are presenting the experimental measurements
of the power consumption and the maximum frequency in an
ASIC prototype of 12 versions of the Trivium cipher: one standard
version and two low power versions (FPLP and ... We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also described the mechanism for measuring power consumption in each Trivium implemented in the ASIC prototype. The clock tree of the ciphers has been designed in such a way that the clock signal of each Trivium can be cut independently. The experimental setup uses the Agilent 93000 testing system. The results show that the higher radix versions have a lower operating frequency and that the lower radix low-power versions have a very high power reduction. However, the Trivium radix-16 versions generate 16 bit/clock cycle so the measurements conclude that the MPLP version is the one with the lowest power consumption per bit (0.69 pJ/bit at 50 MHz). |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | TEC2013-45523-R
TEC2016-80549-R CSIC 201550E039 |
Cita | Mora Gutiérrez, J.M., Jiménez Fernández, C.J. y Valencia Barrero, M. (2020). ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. IEEE Transactions on Circuits and Systems II: Express Briefs, 67 (11), 2682-2686. |
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