dc.creator | Mora Gutiérrez, José Miguel | es |
dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2021-03-15T09:21:14Z | |
dc.date.available | 2021-03-15T09:21:14Z | |
dc.date.issued | 2020 | |
dc.identifier.citation | Mora Gutiérrez, J.M., Jiménez Fernández, C.J. y Valencia Barrero, M. (2020). ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. IEEE Transactions on Circuits and Systems II: Express Briefs, 67 (11), 2682-2686. | |
dc.identifier.issn | 1549-7747 | es |
dc.identifier.uri | https://hdl.handle.net/11441/106025 | |
dc.description.abstract | We are presenting the experimental measurements
of the power consumption and the maximum frequency in an
ASIC prototype of 12 versions of the Trivium cipher: one standard
version and two low power versions (FPLP and MPLP) with
four different radix (radix-1, radix-2, radix-8 and radix-16). It is
also described the mechanism for measuring power consumption
in each Trivium implemented in the ASIC prototype. The clock
tree of the ciphers has been designed in such a way that the clock
signal of each Trivium can be cut independently. The experimental
setup uses the Agilent 93000 testing system. The results show
that the higher radix versions have a lower operating frequency
and that the lower radix low-power versions have a very high
power reduction. However, the Trivium radix-16 versions generate
16 bit/clock cycle so the measurements conclude that the
MPLP version is the one with the lowest power consumption per
bit (0.69 pJ/bit at 50 MHz). | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-45523-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2016-80549-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad CSIC 201550E039 | es |
dc.format | application/pdf | es |
dc.format.extent | 5 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Express Briefs, 67 (11), 2682-2686. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | ASIC implementation | es |
dc.subject | IoT hardware | es |
dc.subject | lightweight cryptography | es |
dc.subject | Low-power | es |
dc.subject | Trivium | es |
dc.title | ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2013-45523-R | es |
dc.relation.projectID | TEC2016-80549-R | es |
dc.relation.projectID | CSIC 201550E039 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8968343 | es |
dc.identifier.doi | 10.1109/TCSII.2020.2969242 | es |
dc.journaltitle | IEEE Transactions on Circuits and Systems II: Express Briefs | es |
dc.publication.volumen | 67 | es |
dc.publication.issue | 11 | es |
dc.publication.initialPage | 2682 | es |
dc.publication.endPage | 2686 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |