dc.creator | Camuñas Mesa, Luis Alejandro | es |
dc.creator | Domínguez Cordero, Yaisel L. | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2020-10-21T08:41:50Z | |
dc.date.available | 2020-10-21T08:41:50Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Camuñas Mesa, L.A., Domínguez Cordero, Y.L., Serrano Gotarredona, M.T. y Linares Barranco, B. (2018). Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA. En ISCAS 2018: IEEE International Symposium on Circuits and Systems Florence, Italy: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-5386-4881-0 | es |
dc.identifier.issn | 2379-447X | es |
dc.identifier.uri | https://hdl.handle.net/11441/102107 | |
dc.description.abstract | We have developed a fully configurable event-driven
convolutional module with refractory period mechanism that can
be used to implement arbitrary Convolutional Neural Networks
(ConvNets) on FPGAs following a 2D array structure. Using this
module, we have implemented in a Spartan6 FPGA a 4-layer
ConvNet with 22 convolutional modules trained for poker card
symbol recognition. It has been tested with a stimulus where 40
poker cards were observed by a Dynamic Vision Sensor (DVS)
in 1s time. A traffic control mechanism is implemented to downsample
high speed input stimuli while keeping spatio-temporal
correlation. For slow stimulus play back, a 96% recognition rate
is achieved with a power consumption of 0.85mW. At maximum
play back speed, the recognition rate is still above 63% when
less than 20% of the input events are processed. | es |
dc.description.sponsorship | European Union's Horizon 2020 644096 (ECOMODE | es |
dc.description.sponsorship | European Union's Horizon 2020 No 687299 NeuRAM | es |
dc.description.sponsorship | Ministerio de Ciencia, Innovación y Universidades TEC2015- 63884-C2-1-P | es |
dc.description.sponsorship | Junta de Andalucía TIC-6091 | es |
dc.format | application/pdf | es |
dc.format.extent | 5 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ISCAS 2018: IEEE International Symposium on Circuits and Systems (2018), | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | ConvNets | es |
dc.subject | Refractory Period | es |
dc.subject | Event-driven processing | es |
dc.subject | Reconfigurable Networks | es |
dc.subject | AER vision | es |
dc.title | Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | 644096 (ECOMODE | es |
dc.relation.projectID | 687299 (NEURAM3) | es |
dc.relation.projectID | TEC2015- 63884-C2-1-P | es |
dc.relation.projectID | TIC-6091 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8351570 | es |
dc.identifier.doi | 10.1109/ISCAS.2018.8351570 | es |
dc.eventtitle | ISCAS 2018: IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Florence, Italy | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | European Union (UE) | es |
dc.contributor.funder | European Union (UE) | es |
dc.contributor.funder | Ministerio de Ciencia, Innovación y Universidades (MICINN). España | es |
dc.contributor.funder | Junta de Andalucía | es |