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dc.creatorCamuñas Mesa, Luis Alejandroes
dc.creatorDomínguez Cordero, Yaisel L.es
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorLinares Barranco, Bernabées
dc.date.accessioned2020-10-21T08:41:50Z
dc.date.available2020-10-21T08:41:50Z
dc.date.issued2018
dc.identifier.citationCamuñas Mesa, L.A., Domínguez Cordero, Y.L., Serrano Gotarredona, M.T. y Linares Barranco, B. (2018). Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA. En ISCAS 2018: IEEE International Symposium on Circuits and Systems Florence, Italy: IEEE Computer Society.
dc.identifier.isbn978-1-5386-4881-0es
dc.identifier.issn2379-447Xes
dc.identifier.urihttps://hdl.handle.net/11441/102107
dc.description.abstractWe have developed a fully configurable event-driven convolutional module with refractory period mechanism that can be used to implement arbitrary Convolutional Neural Networks (ConvNets) on FPGAs following a 2D array structure. Using this module, we have implemented in a Spartan6 FPGA a 4-layer ConvNet with 22 convolutional modules trained for poker card symbol recognition. It has been tested with a stimulus where 40 poker cards were observed by a Dynamic Vision Sensor (DVS) in 1s time. A traffic control mechanism is implemented to downsample high speed input stimuli while keeping spatio-temporal correlation. For slow stimulus play back, a 96% recognition rate is achieved with a power consumption of 0.85mW. At maximum play back speed, the recognition rate is still above 63% when less than 20% of the input events are processed.es
dc.description.sponsorshipEuropean Union's Horizon 2020 644096 (ECOMODEes
dc.description.sponsorshipEuropean Union's Horizon 2020 No 687299 NeuRAMes
dc.description.sponsorshipMinisterio de Ciencia, Innovación y Universidades TEC2015- 63884-C2-1-Pes
dc.description.sponsorshipJunta de Andalucía TIC-6091es
dc.formatapplication/pdfes
dc.format.extent5es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2018: IEEE International Symposium on Circuits and Systems (2018),
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectConvNetses
dc.subjectRefractory Periodes
dc.subjectEvent-driven processinges
dc.subjectReconfigurable Networkses
dc.subjectAER visiones
dc.titleEvent-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGAes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectID644096 (ECOMODEes
dc.relation.projectID687299 (NEURAM3)es
dc.relation.projectIDTEC2015- 63884-C2-1-Pes
dc.relation.projectIDTIC-6091es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8351570es
dc.identifier.doi10.1109/ISCAS.2018.8351570es
dc.eventtitleISCAS 2018: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionFlorence, Italyes
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderMinisterio de Ciencia, Innovación y Universidades (MICINN). Españaes
dc.contributor.funderJunta de Andalucíaes

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