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Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters

 

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Opened Access Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters
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Author: Ruiz Amaya, Jesús
Rosa Utrera, José Manuel de la
Delgado Restituto, Manuel 
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2004
Published in: Conference on Design of Circuits and Integrated Systems (2004), p 39-44
Document type: Presentation
Abstract: This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S-functions. This approach significantly speeds up system- level simulations while keeping high accuracy − verified with HSPICE − and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool.
Cite: Ruiz Amaya, J., Rosa Utrera, J.M.d.l. y Delgado Restituto, M. (2004). Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters. En Conference on Design of Circuits and Integrated Systems, Bordeaux (Francia).
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URI: https://hdl.handle.net/11441/80035

This work is under a Creative Commons License: 
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