dc.creator | Tortosa Navas, Ramón | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.creator | Fernández Fernández, Francisco Vidal | es |
dc.date.accessioned | 2018-11-08T13:15:52Z | |
dc.date.available | 2018-11-08T13:15:52Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | Tortosa Navas, R., Rosa Utrera, J.M.d.l., Rodríguez Vázquez, Á.B. y Fernández Fernández, F.V. (2005). Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC. En Conference on Design of Circuits and Integrated Systems, Lisboa (Portugal). | |
dc.identifier.uri | https://hdl.handle.net/11441/79958 | |
dc.description.abstract | This paper analyses the effect of the clock
jitter error in multi-bit continuous-time ΣΔ modulators
with non-return-to-zero feedback waveform. Derived
expressions show that the jitter-induced noise power can
be separated into two main components: one that
depends on the modulator loop filter transfer function
and the other one due to the input signal parameters, i.e
amplitude and frequency. The latter component, not considered
in previous approaches, allows us to accurately
predict the resolution loss caused by jitter, showing effects
not taken into account up to now in literature which are
specially critical in broadband telecom applications.
Moreover, the use of state-space formulation makes the
analysis quite general and applicable to either cascade or
single-loop architectures. Time-domain simulations of
several modulator topologies intended for VDSL application
are given to validate the presented analysis. | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC2004-01752/MIC, TIC2003-02355 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | Conference on Design of Circuits and Integrated Systems (2005), p 1-6 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2004-01752/MIC | es |
dc.relation.projectID | TIC2003-02355 | es |
idus.format.extent | 6 p. | es |
dc.publication.initialPage | 1 | es |
dc.publication.endPage | 6 | es |
dc.eventtitle | Conference on Design of Circuits and Integrated Systems | es |
dc.eventinstitution | Lisboa (Portugal) | es |
dc.contributor.funder | Ministerio de Educación y Ciencia (MEC). España | |