Opened Access A micropower log domain FGMOS filter
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Author: Rodríguez Villegas, Esther
Rueda Rueda, Adoración
Yúfera García, Alberto
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2002
Published in: ISCAS 2002: IEEE International Symposium on Circuits and Systems (2002), p III-317-III-320
ISBN/ISSN: 0-7803-7448-7
Document type: Presentation
Abstract: In this paper, a CMOS implementation of a low voltage micropower logarithmic biquad based on floating gate MOS transistors (FGMOS) is presented. The translinear principle applied to the floating gate MOS transistor leads to an easy implementation of the state-space equations without using the source terminal in the loop. The voltage supply can be reduced and also there is no need of separate wells. The technique is proven in this low/band pass filter working at 1 V with a maximum power consumption of 2 /spl mu/W. The filter parameters can be adjusted in more than two decades, being the upper frequency around 150 kHz.
Cite: Rodríguez Villegas, E., Rueda Rueda, A. y Yúfera García, A. (2002). A micropower log domain FGMOS filter. En ISCAS 2002: IEEE International Symposium on Circuits and Systems (III-317-III-320), Phoenix-Scottsdale, AZ, USA: IEEE Computer Society.
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URI: https://hdl.handle.net/11441/76012

DOI: 10.1109/ISCAS.2002.1010224

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