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A low-voltage /spl radic/x floating-gate MOS integrator

 

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Opened Access A low-voltage /spl radic/x floating-gate MOS integrator
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Author: Rodríguez Villegas, Esther
Yúfera García, Alberto
Rueda Rueda, Adoración
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2000
Published in: ISCAS 2000: IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (2000), p I-184-I-187
Document type: Presentation
Abstract: In this paper, the design and simulation results of an IV integrator using floating gate MOS (FGMOS) transistor techniques is presented. Combining FGMOS working in strong and in weak inversion a current-mode companding integrator is proposed implemented in a standard CMOS process is able to work with very low supply voltage. It has application in audio signal processing. Simulation results show a very low power consumption (1.3 /spl mu/W), low frequencies below 5 Hz feasible, and a dynamic range of 55 dB for a maximum THD=1.2%. The gain of the integrator is adjustable in more than 2 decades.
Cite: Rodríguez Villegas, E., Yúfera García, A. y Rueda Rueda, A. (2000). A low-voltage /spl radic/x floating-gate MOS integrator. En ISCAS 2000: IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (I-184-I-187), Geneva, Switzerland: IEEE Computer Society.
Size: 295.6Kb
Format: PDF

URI: https://hdl.handle.net/11441/75652

DOI: 10.1109/ISCAS.2000.857058

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