Opened Access Improving speed of tunnel FETs logic circuits

Citas

buscar en

Estadísticas
Icon
Exportar a
Autor: Avedillo de Juan, María José
Nuñez Martínez, Juan
Departamento: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Fecha: 2015
Publicado en: Electronics Letters, 51 (21), 1702-1704.
Tipo de documento: Artículo
Resumen: Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital TFETs circuits leading to delay degradation. In this paper, we propose a minor modification of the complementary gate topology to avoid the bootstrapping problem and show its impact on speed at the circuit level. Speed improvements up to 33% have been obtained for 8-bit Ripple Carry Adders when implemented with our solution.
Cita: Avedillo de Juan, M.J. y Nuñez Martínez, J. (2015). Improving speed of tunnel FETs logic circuits. Electronics Letters, 51 (21), 1702-1704.
Tamaño: 121.6Kb
Formato: PDF

URI: https://hdl.handle.net/11441/72851

DOI: 10.1049/el.2015.2416

Ver versión del editor

Mostrar el registro completo del ítem


Esta obra está bajo una Licencia Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 Internacional

Este registro aparece en las siguientes colecciones