dc.creator | Núñez Martínez, Juan | es |
dc.creator | Avedillo de Juan, María José | es |
dc.date.accessioned | 2018-04-12T16:36:32Z | |
dc.date.available | 2018-04-12T16:36:32Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Nuñez Martínez, J. y Avedillo de Juan, M.J. (2016). Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas. IEEE Journal on Electron Devices, 63 (12), 5012-5020. | |
dc.identifier.issn | 0018-9383 | es |
dc.identifier.uri | https://hdl.handle.net/11441/72621 | |
dc.description.abstract | In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-40670-P | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Journal on Electron Devices, 63 (12), 5012-5020. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Tunnel transistors | es |
dc.subject | Steep subthreshold slope | es |
dc.subject | Low power | es |
dc.subject | Energy efficieny | es |
dc.subject | Low supply voltage | es |
dc.title | Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2013-40670-P | es |
dc.relation.publisherversion | https://doi.org/10.1109/TED.2016.2616891 | es |
dc.identifier.doi | 10.1109/TED.2016.2616891 | es |
idus.format.extent | 8 p. | es |
dc.journaltitle | IEEE Journal on Electron Devices | es |
dc.publication.volumen | 63 | es |
dc.publication.issue | 12 | es |
dc.publication.initialPage | 5012 | es |
dc.publication.endPage | 5020 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | |