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On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Opened Access On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

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Autor: Yousefzadeh, Amirreza
Jabłonski, M.
Iakymchuk, T.
Linares Barranco, Alejandro
Rosado, Alfredo
Plana, Luis A.
Temple, Steve
Serrano Gotarredona, María Teresa
Furber, Steve B.
Linares Barranco, Bernabé
Departamento: Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores
Fecha: 2017
Publicado en: IEEE Transactions on Biomedical Circuits and Systems, 11 (5), 1133-1147.
Tipo de documento: Artículo
Resumen: Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs...
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Cita: Yousefzadeh, A., Jabłonski, M., Iakymchuk, T., Linares Barranco, A., Rosado, A., Plana, L.A.,...,Linares Barranco, B. (2017). On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. IEEE Transactions on Biomedical Circuits and Systems, 11 (5), 1133-1147.
Tamaño: 4.128Mb
Formato: PDF

URI: https://hdl.handle.net/11441/72615

DOI: 10.1109/TBCAS.2017.2717341

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