Artículo
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems
Autor/es | Yousefzadeh, Amirreza
Jabłonski, M. Iakymchuk, T. Linares Barranco, Alejandro Rosado, Alfredo Plana, Luis A. Temple, Steve Serrano Gotarredona, María Teresa Furber, Steve B. Linares Barranco, Bernabé |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2017 |
Fecha de depósito | 2018-04-12 |
Publicado en |
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Resumen | Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is ... Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available. |
Identificador del proyecto | 320689
604102 644096 687299 EP/G015740/1 11.11.120.612 TEC2012-37868-C04-01/02 TEC2015- 63884-C2-1-P TEC2016-77785-P TIC-6091 P12-TIC-1300 |
Cita | Yousefzadeh, A., Jabłonski, M., Iakymchuk, T., Linares Barranco, A., Rosado, A., Plana, L.A.,...,Linares Barranco, B. (2017). On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. IEEE Transactions on Biomedical Circuits and Systems, 11 (5), 1133-1147. |
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