dc.creator | Pettenghi Roldán, Héctor | es |
dc.creator | Avedillo de Juan, María José | es |
dc.creator | Quintana Toledo, José María | es |
dc.date.accessioned | 2017-12-27T17:21:30Z | |
dc.date.available | 2017-12-27T17:21:30Z | |
dc.date.issued | 2011 | |
dc.identifier.citation | Pettenghi Roldán, H., Avedillo de Juan, M.J. y Quintana Toledo, J.M. (2011). Improved nanopipelined RTD adder using generalized threshold gates. IEEE Transactions on Nanotechnology, 10 (1), 155-162. | |
dc.identifier.issn | 1536-125X (impreso) | es |
dc.identifier.uri | http://hdl.handle.net/11441/68026 | |
dc.description.abstract | Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from thres hold gates (TGs). This paper describes the design of full adders (FAs) using TG based circuit topologies. Both the selection of different MOBILE TG networks and the use of gates that can be considered
extensions of the MOBILE TG are addressed. The FAs are applied to the design of nanopipelined carry propagations adders which are evaluated and compared to a previously reported one, showing advantages in terms
of speed, power and power delay product. | es |
dc.description.sponsorship | Gobierno de España TEC2007-67245 | es |
dc.description.sponsorship | Gobierno de Andalucía EXC/2007/TIC-2961 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Nanotechnology, 10 (1), 155-162. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Resonant Tunneling Diodes | es |
dc.subject | MOBILE | es |
dc.subject | Threshold gate | es |
dc.subject | Nanopipelining | es |
dc.subject | Adder | es |
dc.title | Improved nanopipelined RTD adder using generalized threshold gates | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2007-67245 | es |
dc.relation.projectID | EXC/2007/TIC-2961 | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TNANO.2009.2035311 | es |
dc.identifier.doi | 10.1109/TNANO.2009.2035311 | es |
idus.format.extent | 28 p. | es |
dc.journaltitle | IEEE Transactions on Nanotechnology | es |
dc.publication.volumen | 10 | es |
dc.publication.issue | 1 | es |
dc.publication.initialPage | 155 | es |
dc.publication.endPage | 162 | es |
dc.identifier.sisius | 6518778 | es |
dc.contributor.funder | Gobierno de España | |
dc.contributor.funder | Junta de Andalucía | |