dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Guerrero Martos, David | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.date.accessioned | 2017-01-20T10:06:03Z | |
dc.date.available | 2017-01-20T10:06:03Z | |
dc.date.issued | 2003 | |
dc.identifier.citation | Millán Calderón, A., Bellido Díaz, M.J., Juan Chico, J., Guerrero Martos, D., Ruiz de Clavijo Vázquez, P. y Ostua Arangüena, E. (2003). Internode: Internal Node Logic Computational Model. En 36th Annual Simulation Symposium (ANSS-36 2003) (241-248), Orlando, Florida: IEEE Computer Society. | |
dc.identifier.isbn | 0-7695-1911-3 | es |
dc.identifier.issn | 1080-241X | es |
dc.identifier.uri | http://hdl.handle.net/11441/52523 | |
dc.description.abstract | In this work, we present a computational behavioral
model for logic gates called Internode (Internal Node Logic
Computational Model) that considers the functionality of
the gate as well as all the different internal states the gate
can reach. This computational model can be used in logiclevel
tools and is valid for any dynamic behavioral model
(delay models, power models, switching noise models, etc.).
Also, we show a very efficient implementation of the model,
in C language, for -inputs SCMOS NOR/NAND gates. Finally,
we demonstrate the functionality of the model showing
three different examples of modeling: (a) a propagation
delay model, (b) the degradation delay model (DDM), and
(c) a simple power model | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Internode: Internal Node Logic Computational Model | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TIC 2000-1350 | es |
dc.relation.projectID | TIC 2002-2283 | es |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1192819/ | es |
dc.identifier.doi | 10.1109/SIMSYM.2003.1192819 | es |
idus.format.extent | 8 | es |
dc.publication.initialPage | 241 | es |
dc.publication.endPage | 248 | es |
dc.eventtitle | 36th Annual Simulation Symposium, ANSS-36 | es |
dc.eventinstitution | Orlando, Florida | es |
dc.relation.publicationplace | USA | es |