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A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors

Opened Access A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors

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Autor: Suárez, M.
Brea, V. M.
Pardo, F.
Carmona Galán, R.
Rodríguez Vázquez, Ángel Benito
Departamento: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Fecha: 2012
Publicado en: IEEE International 3D Systems Integration Conference 2012.Osaka), 1-8
ISBN/ISSN: 978-1-4673-2189-1
Tipo de documento: Ponencia
Resumen: This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which in turn can be used for operations like object detection, image registration or tracking. The top tier of the architecture contains the image acquisition circuits in an array of 320 × 240 active photodiode sensors (APS) driving a smaller array of 160 × 120 analog processors for low-level image processing. The top tier comprises in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel Analog to Digital Converter (ADC). The reuse of circuits for different functions permits to have a small area for every pixel. The bottom tier of the architecture contains a frame buffer with a set of registers acting as a frame-buffer with a one-to-one correspondence with the analog processor...
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Cita: Suárez, M., Brea, V.M., Pardo, F., Carmona Galán, R. y Rodríguez Vázquez, Á.B. (2012). A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors. Institute of Electrical and Electronics Engineers.
Tamaño: 6.256Mb
Formato: PDF

URI: http://hdl.handle.net/11441/33652

DOI: http://dx.doi.org/10.1109/3DIC.2012.6263019

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