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A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors

 

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Opened Access A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors
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Author: Suárez, M.
Brea, Víctor M.
Pardo, F.
Carmona Galán, Ricardo
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2012
Published in: IEEE International 3D Systems Integration Conference 2012.Osaka), 1-8
ISBN/ISSN: 978-1-4673-2189-1
Document type: Presentation
Abstract: This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which in turn can be used for o...
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Cite: Suárez, M., Brea, V.M., Pardo, F., Carmona Galán, R. y Rodríguez Vázquez, Á.B. (2012). A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors. Institute of Electrical and Electronics Engineers.
Size: 6.256Mb
Format: PDF

URI: http://hdl.handle.net/11441/33652

DOI: http://dx.doi.org/10.1109/3DIC.2012.6263019

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