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Ponencia
On the AER Convolution Processors for FPGA
(IEEE Computer Society, 2010)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these ...
Ponencia
AER tools for Communications and Debugging
(IEEE Computer Society, 2006)
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them ...
Ponencia
AER image filtering
(SPIE Digital LIbrary, 2007-05)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows realtime virtual massive connectivity among huge number of neurons located on different chips [1]. By exploiting ...
Ponencia
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
(Springer, 2009)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In ...
Ponencia
High-speed image processing with AER-based components
(IEEE Computer Society, 2006)
A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions/sec) ...
Ponencia
An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata
(Springer, 2011)
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event- Representation (AER) is a neuromorphic communication protocol for ...
Ponencia
Live Demonstration: real time objects tracking using a bio-inspired processing cascade architecture
(IEEE Computer Society, 2010)
This demonstration shows how a new bio-inspired processing cascade architecture is used for simultaneous objects tracking.
Ponencia
Implementation of a time-warping AER mapper
(IEEE Computer Society, 2009)
In recent implementations of neuromorphic spikebased sensors, multi-neuron processors, and actuators; the spike traffic between devices is coded in the form of asynchronous spike streams following the Address-Event-Re ...
Artículo
A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
(IEEE Computer Society, 2017)
This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital ...
Ponencia
Diseño de material específico docente para el aprendizaje de microcontroladores y sistemas USB
(AENUI: Asociación de Enseñantes Universitarios de Informática, 2011)
En la enseñanza en profundidad y especializada en materias de tipo informática nos encontramos con que los contenidos no paran de crecer y cada vez son más difíciles de abarcar. Por otra parte hay que empezar a pensar ...